Process for compensating component tolerances in analog-digital converters

ABSTRACT

A method for the compensation of component tolerances of a number of similar components, in particular capacitors in analog-to-digital converters which are connected to a common line, and whose electric value is in each case halved from component to component, the component with the smallest value being present twice. In this method, a first potential is at first applied to at least one of the components and a second potential is applied to the remaining components with lower values. A comparator then checks whether on the common line the mid-potential between the two potentials is present. There is then applied to a correction component (which is in addition connected to the common line) a variable correction voltage which is adjusted until the comparator determines the mid-potential on the common line. The determined correction voltage is finally stored as a correction value. As a result, each of these components can be adjusted individually and tolerance errors can be equalized, individual recalibrations being possible in each case which interrupt the converter operation of the analog-to-digital converter only for a very brief period. The precision and linearity of an analog-to-digital converter which uses a capacitor array adjusted in this way are very high.

FIELD OF THE INVENTION

The invention relates to a method for the compensation of componenttolerances of a number of similar components, such as capacitors,resistors, current sources and the like, in analog-to-digitalconverters.

BACKGROUND INFORMATION

The short-channel CMOS processes usually used during the production ofanalog-to-digital converters are optimized to high transistor componentdensities and high switching speeds. In particular in the area of ASICdesign, however, the further processing of an item of analog inputinformation increasingly requires high-resolution and also preciseanalog-to-digital converters. As a result of how the process is carriedout, high-precision analog components, such as for example resistors andcapacitors, are available only in very rare cases. Therefore, in orderto achieve accuracies beyond the limit of 8 bits, an adjustment methodhas to be provided, the type of adjustment essentially determining thequality and reliability of the converter. Binary weighted capacitorarrays are often used in analog-to-digital converters. However,inaccuracies in the weighting ratio of the capacitances inevitably leadto faulty conversion results. These errors result in differentialnonlinearities (DNL) which often exceed the specified framework. A12-bit converter can for example be specified with a precision of 1/2 or1/4 LSB, it being possible that discrepancies in the capacitive arraywhich controls the upper 8 bits lead to faults of a couple of 10 LSB.

The following printed publications:

(1) LEE H.S., Hodges D.A., "Self-Calibration Technique for A/Dconverter", IEEE CAS-30, pp. 188-190, March 1983

(2) Tsukada T., Takagi K., Kita Y., Nagata M., "An Automatic ErrorCancellation Technique for Higher Accuracy A/D Converters", IEEE,Journal of Solid-State-Circuits, Vol. SC-19, No. 2, pp. 266-268, April1984

(3) Matsuya Y., Akazawa Y., Iwata A., "High-Linearity and High-SpeedCMOS 1-chip A/D, D/A Converter. All-Digital Linearity Error Correction(LECS)", Electronics and Communications in Japan, Part 2, Vol. 70, pp.73-84, 1987

(4) McCreary J. L., Gray P. R., "A High-Speed, All-MOS SuccessiveApproximation Weighted Capacitor A/D Conversion Technique" ISSCC Dig.Tech. Papers, pp. 38-39, February 1975

(5) McCreary J. L., Gray P. R., "All-MOS Charge RedistributionAnalog-to-Digital Conversion Techniques-Part I", IEEE SC-10 pp. 371-379,December 1979

disclose correction methods for capacitance arrays in analog-to-digitalconverters, all of which use an additional digital-to-analog converter.In the case of known correction methods, the capacitor array iscorrected in its entirety, but not the individual capacitancesindependently of the capacitance deviations of the others. Consequently,a recalibration is not possible during normal operation without arelatively long interruption of the conversion process.

European Patent Application No. 0 064 147 A3 describes ananalog-to-digital converter in which a multiplicity of similarcapacitors are used, where the capacitance values are in each casehalved from component to component. The component with the smallestplace value is present twice. By applying potentials, a predeterminedcomponent is compared with the remaining components of lower place valuein that the potential which then appears at the capacitors is comparedwith a reference potential. In this process, all capacitors are comparedwith each other successively.

SUMMARY OF THE INVENTION

The compensation method according to the invention has the advantagethat as a result of the individual corrections of the individualcomponents, in particular capacitors, independently of the othercomponents, a recalibration of each individual component is possibleduring normal operation, in each case only very short interruptions ofthe conversion process being required for this purpose. In addition, theindividual compensation of tolerances of the individual componentsleads, on the whole, to a very precise analog-to-digital conversion overthe entire range.

Particularly advantageous is the repetition of the method withinterchanged first and second potential, the implementation of amean-value formation of the two determined correction voltages and thestorage of the mean value as the correction value. Possible inaccuraciesof the mid-potential are automatically compensated thereby, with theresult that the formation of the mid-potential can likewise be carriedout relatively inaccurately and have no effect on the precision of theanalog-to-digital conversion.

It is expedient for a correction value to be determined and stored in acorresponding manner for each component, preferably in digital form.

An advantageous design of the compensation adjustment by the comparatorcan be performed in that the correction voltage is formed as a changingsignal sequence with a small voltage change and in that a correspondingoutput signal change at the comparator is evaluated as an adjustmentwhich has been achieved. In order to achieve continuous recalibrationduring the normal operation of the analog-to-digital converter, arecalibration of the correction values is performed during operationalinterruptions of the analog-to-digital converter one after the other, atleast one correction value being recalibrated during each operationalinterruption. Of course, it is also possible to recalibrate allcorrection values during a break in the work or an operationalinterruption or on demand.

In order to equalize significant differences of the newly determinedcorrection values during the recalibration process, a smoothing methodfor attenuating these types of differences in the manner of a low-passfilter is advantageously provided. Large deviations which are possiblybased on disturbances can be prevented thereby.

During proper operation of the analog-to-digital converter, the storedcorrection values are accordingly taken into account one after the otherduring each conversion step, so that each conversion step is carried outwith the highest possible precision.

In order to achieve defined starting conditions, all the componentswhich are designed as capacitors are discharged before the determinationor recalibration of correction values. For this purpose, in particularboth connections are connected to the mid-potential.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an analog-to-digital converter with acompensation device according to the present invention.

FIG. 2 shows a capacitor array in conjunction with required switches forcarrying out the analog-to-digital conversion and the compensationprocess, according to the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In the analog-to-digital converter illustrated in FIG. 1, a capacitorarray 10 provided with a multiplicity of switches is controlled by acontrol unit 11 (memory selection register and array driver). Thecapacitor array 10 has at the output side a comparator 12 whichintervenes both in the control unit 11 and in a calibration andcorrection module 13, hereafter designated in a simplified way as module13. This module 13 intervenes, via a correction digital-to-analogconverter 14, in the capacitor array 10 and supplies in particular acorrection voltage Vk, as will be explained in even more detail in thefollowing text. This correction digital-to-analog converter 14 ishereafter designated in a simplified way as D/A converter 14. A centralcontroller 15 which contains, in a manner not shown but known in theart, a clock decoder controlling the central functions of the controlunit 11 and of the module 13. In addition, the control unit 11 and themodule 13 influence each other.

In FIG. 2, the capacitor array 10 essentially comprising ten capacitors,to be specific a correction capacitor Ck and nine working capacitorsCla, Clb as well as C2 to C8. The capacitor C8 has the highestcapacitance, in each case the following capacitor having a capacitancehalf as large as the next. The two capacitors Cla and Clb have identicalcapacitance values which represent the smallest capacitance values.

All capacitors are connected to a common center line 16 which isconnected via the comparator. 12 to the control unit 11 and to themodule 13. For reasons of simplification, the capacitors C3 to C7 arenot illustrated. The number of working capacitors determines theprecision of the analog-to-digital converter, that is to say its bitresolution.

The analog input voltage Vi to be converted into digital values is fedvia a controllable switch 17 to the capacitor array 10, this switch 17being connected via further controllable switches 18-22 to all thecapacitors (of course also to the capacitors C3 to C7, which are notillustrated, via further switches which are not illustrated). An uppervoltage potential Vdd can be applied via further switches 23 to 26 tothe working capacitors Cla to C8. Finally, another lower potential Vsscan be applied via the switches 27 to 30 to the working capacitors Clato C8. A mid-potential Vm which represents a mean value between thepotentials Vdd and Vss can be applied, via a further switch 31, to thecenter line 16 and, via a further switch 32, to the line to which theanalog input voltage Vi is fed (via the switch 17). The correctionvoltage Vk can be fed to the correction capacitor Ck via a switch 33.Instead of the arrangement illustrated, the mid voltage Vm can also befed to this correction capacitor Ck separately via the switch 18, thus amid voltage which is produced independently of the mid voltage which canbe applied to the center line 16. In practice, connection of anindependent mid voltage is often realized using this alternatearrangement.

With the exception of the compensation of component tolerance, which isstill to be explained, the mode of operation of this type ofanalog-to-digital converter is known from the prior art and willtherefore be discussed only briefly. At first, the input voltage Vi isapplied to all working capacitors Cla to C8 by closing the switches 17,19 to 22, while the mid-potential Vm is present at the oppositeconnections by closing the switch 31. All switches are now opened againand the switches 26 and 27 to 29 are then closed. As a result, the uppervoltage Vdd is present at the capacitor C8 having the highestcapacitance and the lower voltage Vss at the remaining capacitors. If apotential is present at the center line 16 which is higher in comparisonto the mid-potential Vm , the comparator 12 responds, the switch 26 isopened again and the switch 30 is closed for the remaining conversiontime. The voltage Vdd is now applied to the next lower capacitor C7 (notshown) instead of the voltage Vss. Here, again, it is monitored whetheror not the comparator 12 responds. If it does not respond, the voltageVdd remains applied to this capacitor C7 and the potential Vdd isapplied to the next capacitor C6 instead of the potential Vss. In eachiteration the comparator 12 is checked for a response, and if itresponds, the voltage Vdd is disconnected and the associated switch toVss is secured, as already explained, for the further conversion time,otherwise the voltage Vdd remains applied to the respective capacitor.After this process has been carried out for all Capacitors Cla to C8,the switch positions of the switches to which the potential Vdd can beapplied yield the digital word which corresponds to the analog inputvoltage Vi. This digital word is passed via the comparator 12 inaccordance with the respective steps into the control unit 11 for lateroutput to connected devices.

The precision of the analog-to-digital conversion described isdetermined in particular by the precision of the capacitance values ofthe capacitors. Since the desired precision can, in practice, never beachieved with justifiable outlay, a compensation of the tolerances ofthese capacitors is now carried out. For this purpose, the switch 17 isconstantly open since the analog input voltage is not relevant for thisprocess. At first, all capacitors are discharged. This is carried out byclosing the switches 18 to 22 and 31 and 32. As a result, themid-potential Vm is present on both connections of all capacitors. Thismid-potential Vm represents the mid-potential between the potentials Vddand Vss and can be formed for example by a voltage divider. In thisprocess, the precision is of no importance, as will be explained later.

All switches are then opened again and the switches 27 to 29 and 26 arethen closed. As a result, the higher voltage Vdd is present at thecapacitor C8 having the greatest capacitance and the lower voltage Vssis present at the remaining working capacitors Cla to C7. If allcapacitance values were exactly correct, the midpotential Vm exactlywould now be present at the center line 16 since the sum of thecapacitance values of the capacitors Cla to C7 corresponds to thecapacitance of C8. Such an exact charge division could be achieved onlyin the case of a perfect, binary weighted capacitance arrangement. Eachscattering of the capacitance values of the capacitors of the arrayleads inevitably to a deviation from the ideal mid-potential. Thisdeviation is determined by means of the comparator 12 which compares thepotential which appears on the center line 16 with the mid-potential Vm.After a conversion cycle has been carried out completely, a changingsignal with a small voltage change, for example ±1/2 LSB, issuperimposed on the mid-potential which has appeared on the center line16. If a corresponding changing signal is determined at the output ofthe comparator 12, the present adjustment value is correct. Otherwisethe output is at one of the two possible signal levels, as a result ofwhich there is produced via the module 13 a correction signal which isconverted in the D/A converter 14 into an analog correction voltage Vkand fed via the closed switch 33 to the correction capacitor Ck. Thiscorrection voltage Vk is varied until the adjustment is found. Thecorresponding correction signal is stored as a digital correction valuein a memory 34 of the module 13 as the first provisional correctionvalue.

The switches 27 to 29 and 26 are now opened and the switches 23 to 25and 30 are closed instead. The voltage Vss is now present at thecapacitor C8 as a result and the voltage Vdd at the remainingcapacitors. A further corresponding adjustment is then carried out andthe determined correction value is stored as the second provisionalcorrection value. If the mid-potential Vm, evaluated as the comparisonvoltage by the comparator 12, were the exact ideal mid-potential, thetwo provisional correction values would be identical. In the case of adeviation from the ideal mid-potential, the provisional correctionvalues deviate from each other as well. Now the mean value between thetwo provisional correction values is formed and this mean value has tobe stored as the exact correction value for the highest capacitor C8. Inthis way, deviations of the voltage Vm from the ideal mid voltage arecompensated for automatically.

The procedure previously described is then carried out in acorresponding manner for the remaining working capacitors Cla to C7, sothat, in the end, nine correction values are present in the end whichare stored in the memory 34 at the address which is associated with theworking capacitor to be corrected.

After the calibration has been carried out, the control unit 11, whicheffects inter alia the switch control in the capacitor array 10,switches the analog-to-digital converter into the operational state"convert". During this state, it functions in the manner described inthe introduction. In this process, a recalibration can be requested bymeans of an internal time control or on demand from outside. Such arecalibration is carried out sequentially, starting with the top bit,but only the recalibration of one capacitor in each case for eachrequest. The conversion cycle is interrupted only briefly in this way.Of course, it is also possible in principle to carry out a completerecalibration cyclically or on request. For the recalibration process, asmoothing algorithm is provided which attentuates significantdifferences in the respectively found correction value, in a similarmanner to a low-pass filter function. This prevents extreme deviationswhich are formed, for example, by disturbances, affecting the conversionprocess to a serious degree.

It should also be noted that the invention is, of course, not limited tothe calibration or compensation of tolerances of capacitors. Acorresponding compensation can also be carried out for other componentsof an analog-to-digital converter arranged in an array, for exampleresistors, current sources or the like. For example in the case ofresistors, the resistor having the highest conductance corresponds hereto the capacitor having the highest capacitance.

For the purpose of additional explanation, the calibration methoddescribed is also illustrated in the following text in its mathematicalform. The correction voltage Vk, which is formed in the case of an idealmid-voltage Vm for compensation, is described by the following equation(1): ##EQU1##

Here, C (i) is the capacitance to be calibrated, C (j) are allcapacitances with a lower weighting and Ck is the correctioncapacitance. The prefix here Δ represents in each case the deviationfrom the ideal value.

The following equation (2) describes the resulting correction voltageVk', taking into account a deviation of Vm from the ideal value and withthe top capacitance C8 being wired to Vdd and the remaining capacitancesto Vss: ##EQU2##

The following equation (3) describes the resulting correction voltageVk" in the case of an inverse wiring of the capacitances (interchange ofVdd and Vss): ##EQU3##

The mean value of equations (2) and (3) leads to the correct correctionvoltage Vk in accordance with equation (4) by means of which thecorrection capacitor Ck is charged: ##EQU4##

As has already been set out, the digital word assigned to this voltageis stored in the memory 34 at the address of the respectively calibratedcapacitor. The correction word associated with the respective bit isthus always available. The associated correction voltage is fed inadvance during converter operation in the respective bit stage to thecorrection algorithm which is described by the following equations (5)to (7): ##EQU5##

In this case, V (Reg (i, high)) is the weighted sum of the correctionvoltages for which the comparator has so far decided with the outputlevel HIGH. This value is stored in an auxiliary register of the module13. V (Reg (i, low)) is the weighted sum of the correction voltages forwhich the comparator 12 has so far decided with the output level LOW.This value is stored in a working register, for example in the memory34. The equivalent digital word is intermediately stored, and when thecorrection value is identified as being valid, the word is finallystored in the memory 34. V (Corr, i) is the calculated correctionvoltage for the comparator decision in the case of bit i. n is thenumber of bits. Bj and Bj denote the comparator decision of the bit j.

During the evaluation of Cj, if

the comparator was low: Bj=0 and Bj=1

the comparator was high: Bj=1 and Bj=0.

What is claimed is:
 1. A method for compensating at least one componenttolerance of a plurality of similar components in an analog-to-digitalconverter, the components being coupled to a common line, an electricvalue of each component being halved from component to component, acomponent with a smallest electric value being present twice, comprisingthe steps of:(a) applying a first potential to a predetermined componentselected from the plurality of components, and a second potential to allof the components whose electric value is less than the electric valueof the predetermined component; (b) comparing, using a comparator, apotential present on the common line to a mid-potential, themid-potential having an amplitude between the first potential and thesecond potential; (c) applying a variable correction voltage, derivedfrom an output of the comparator, to a correction component coupled tothe common line; (d) adjusting the variable correction voltage until thecomparator determines the presence of the mid-potential on the commonline; and (e) storing a correction value determined from the adjustedvariable correction voltage.
 2. The method according to claim 1, furthercomprising the steps of:repeating steps (a) through (e) interchangingthe first and second potentials; forming a mean value of the correctionvalue produced by the first performance of the method and the correctionvalue produced by the repeated performance; and storing the mean valueas the correction value.
 3. The method according to claim 1, furthercomprising the step of repeating steps (a) through (e) for each of theplurality of components and storing a plurality of correction valuescorresponding respectively to each of the plurality of similarcomponents.
 4. The method according to claim 3, further comprising thestep of performing a recalibration of at least one of the plurality ofcorrection values during an operational interruption of theanalog-to-digital converter.
 5. The method according to claim 3, furthercomprising the step of performing a recalibration of all of theplurality of correction values during a break or on demand.
 6. Themethod according to claim 3, further comprising the step of carrying outa smoothing technique for damping differences in the plurality ofcorrection values, using a low-pass filter.
 7. The method according toclaim 3, further comprising the step of taking into account each of theplurality of correction values during each step of a conversionperformed during normal operation of the analog-to-digital converter. 8.The method according to claim 1, wherein the correction value is storedin digital form.
 9. The method according to claim 1, further comprisingthe steps of sending a changing signal sequence to the comparator forevaluation, determining whether a corresponding output signal change hasoccurred, and deriving the variable correction voltage from thecorresponding output signal change.
 10. The method according to claim 1,wherein the plurality of components include at least one firstcapacitor, and the correction component includes a second capacitor. 11.The method according to claim 10, further comprising the step ofdischarging the plurality of components and the correction componentbefore determining the correction value.
 12. The method according toclaim 11, wherein discharge is achieved by connecting both connectionsof each of the plurality of components to the mid-potential.